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rev. 0.3 6/07 copyright ? 2007 by silicon laboratories SI570/si571 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI570/si571 p reliminary d ata s heet a ny -r ate i 2 c p rogrammable xo/vcxo features applications description the SI570 xo/si571 vcxo utilizes silicon laboratories? advanced dspll ? circuitry to provide a low-jitter clock at any frequency. the SI570/si571 are user-programmable to any output frequency from 10 to 945 mhz and select frequencies to 1400 mhz with <1 ppb resolution. the device is programmed via an i 2 c serial interface. unlike traditional xo/vcxos where a different crystal is required for each output frequency, the si57x uses one fixed- frequency crystal and a dspll clock synthesis ic to provide any-rate frequency operation. this ic-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. in addition, dspll clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. functional block diagram any-rate programmable output frequencies from 10 to 945 mhz and select frequencies to 1.4 ghz i 2 c serial interface 3rd generation dspll ? with superior jitter performance 3x better frequency stability than saw-based oscillators internal fixed crystal frequency ensures high reliability and low aging available lvpecl, cmos, lvds, and cml outputs industry-standard 5x7 mm package pb-free/rohs-compliant 1.8, 2.5, or 3.3 v supply sonet / sdh xdsl 10 gbe lan / wan low-jitter clock generation optical modules clock and data recovery fixed frequency xo any-rate 10-1400 mhz dspll ? clock synthesis clk- clk+ scl gnd oe v dd sda v c adc si571 only ordering information: see page 21. pin assignments: see page 20. (top view) si5602 SI570 si571 1 2 3 6 5 4 nc gnd oe v dd clk+ clk? sda scl 8 7 1 2 3 6 5 4 v c gnd oe v dd clk+ clk? sda scl 8 7
SI570/si571 2 rev. 0.3
SI570/si571 rev. 0.3 3 t able of c ontents section pag e 1. detailed block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.1. frequency programming summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2. frequency programming details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3. i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4. serial port regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. SI570 (xo) pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. si571 (vcxo) pin d escriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 8. si57x mark speci fication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9. outline diagram and suggest ed pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10. 8-pin pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SI570/si571 4 rev. 0.3 1. detailed block diagrams figure 1. SI570 detailed block diagram figure 2. si571 detailed block diagram frequency control control interface nvm hs_div n1 + dco rfreq clkout+ clkout? v dd gnd f xtal f osc m sda oe scl ram frequency control control interface nvm hs_div n1 + dco adc rfreq vcadc v c clkout+ clkout? v dd gnd f xtal f osc m sda oe scl ram
SI570/si571 rev. 0.3 5 2. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max units supply voltage 1 v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 1.8 v option 1.71 1.8 1.89 supply current i dd output enabled lvpecl cml lvds cmos ? ? ? ? 120 108 99 90 130 117 108 98 ma tristate mode ? 60 75 output enable (oe) 2 v ih 0.75 x v dd ?? v v il ??0.5 operating temperature range t a ?40 ? 85 oc notes: 1. selectable parameter specified by part number. see section "7. ordering information" on page 21 for further details. 2. oe pin includes a 17 k pullup resistor to v dd or a 17 k pulldown to gnd depending on the oe polarity specified in the part number. see "7. ordering information" on page 21. table 2. v c control voltage input parameter symbol test condition min typ max units control voltage tuning slope 1,2,3 k v v c 10 to 90% of v dd ? 33 45 90 135 180 356 ? ppm/v control voltage linearity 4 l vc bsl ?5 1 +5 % incremental ?10 5 +10 modulation bandwidth bw 9.3 10.0 10.7 khz v c input impedance z vc 500 ? ? k nominal control voltage v cnom @ f o ?v dd /2 ? v control voltage tuning range v c 0v dd v notes: 1. positive slope; selectable option by part number. see "7. ordering information" on page 21. 2. for best jitter and phase noise performance, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. k v variation is 10% of typical values. 4. bsl determined from deviation from best straight line fit with v c ranging from 10 to 90% of v dd . incremental slope determined with v c ranging from 10 to 90% of v dd .
SI570/si571 6 rev. 0.3 table 3. clk output frequency characteristics parameter symbol test condition min typ max units programmable frequency range 1,2,3 f o lvpecl/lvds/cml 10 ? 945 mhz cmos 10 ? 160 temperature stability 1,4 t a = ?40 to +85 oc ?20 ?50 ?100 ? ? ? +20 +50 +100 ppm aging f a frequency drift over first year ? ? 3 ppm frequency drift over 15 year life ? ? 10 ppm total stability temp stability = 20 ppm ? ? 31.5 ppm temp stability = 50 ppm ? ? 61.5 ppm absolute pull range 1,4 apr 25 ? 375 ppm power up time 5 t osc ??10ms settling time after frequency change t frq f 1 within 100 ppm of f 0 ? ? 100 s f 1 > 100 ppm of f 0 ??10ms notes: 1. see section "7. ordering information" on page 21 for further details. 2. specified at time of order by part number. also available in frequencies from 970 to 1134 mhz and 1213 to 1417 mhz. 3. nominal output frequency set by v cnom =1/2xv dd . 4. selectable parameter specified by part number. 5. time from power up or tristate mode to f o .
SI570/si571 rev. 0.3 7 table 4. clk output levels and symmetry parameter symbol test condition min typ max units lvpecl output option 1 v o mid-level v dd ? 1.42 ? v dd ? 1.25 v v od swing (diff) 1.1 ? 1.9 v pp v se swing (single-ended) 0.55 ? 0.95 v pp lvds output option 2 v o mid-level 1.125 1.20 1.275 v v od swing (diff) 0.5 0.7 0.9 v pp cml output option 2 v o mid-level ? v dd ? 0.75 ? v v od swing (diff) 0.70 0.95 1.20 v pp cmos output option 3 v oh i oh =32ma 0.8 x v dd ? v dd v v ol i ol =32ma ? ? 0.4 rise/fall time (20/80%) t r, t f lvpecl/lvds/cml ? ? 350 ps cmos with c l =15pf ? 1 ? ns symmetry (duty cycle) sym lvpecl: v dd ? 1.3 v (diff) lvds: 1.25 v (diff) cmos: v dd /2 45 ? 55 % notes: 1. 50 to v dd ? 2.0 v. 2. r term =100 (differential). 3. c l =15pf table 5. clk output phase jitter (SI570) parameter symbol test condition min typ max units phase jitter (rms)* for f out > 500 mhz j 12 khz to 20 mhz (oc-48) ? 0.25 0.40 ps 50 khz to 80 mhz (oc-192) ? 0.26 0.37 phase jitter (rms)* for f out of 125 to 500 mhz j 12 khz to 20 mhz (oc-48) ? 0.36 0.50 ps 50 khz to 20 mhz (oc-192) ? 0.34 0.42 *note: differential modes: lvpecl/ lvds/cml. refer to an25 6 for further information.
SI570/si571 8 rev. 0.3 table 6. clk output phase jitter (si571) parameter symbol test condition min typ max units phase jitter (rms) 1,2,3 for f out > 500 mhz j kv = 33 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.26 0.26 ? ? ps kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.27 0.26 ? ? kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.32 0.26 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.40 0.27 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.49 0.28 ? ? kv = 356 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.87 0.33 ? ? notes: 1. differential modes: lvpecl/lvds/cml. refer to an255, an256, and an266 for further information. 2. for best jitter and phase noise performanc e, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. see ?an255: replacing 622 mhz vcso devices with the si550 vcxo? for comparison highlighting power supply rejection (psr) advantage of si55x versus saw-based solutions.
SI570/si571 rev. 0.3 9 phase jitter (rms) 1,2,3 for f out of 125 to 500 mhz j kv = 33 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.37 0.33 ? ? ps kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.37 0.33 ? ? kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.43 0.34 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.50 0.34 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.59 0.35 ? ? kv = 356 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 1.00 0.39 ? ? table 7. clk output period jitter parameter symbol test condition min typ max units period jitter* j per rms ? 2 ? ps peak-to-peak ? 14 ? *note: any output mode, incl uding cmos, lvpecl, lvds, cml. n = 1000 cycles. re fer to ?an279: estima ting period jitter from phase noise? fo r further information. table 6. clk output phase jitter (si571) (continued) parameter symbol test condition min typ max units notes: 1. differential modes: lvpecl/lvds/cml. refer to an255, an256, and an266 for further information. 2. for best jitter and phase noise performanc e, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. see ?an255: replacing 622 mhz vcso devices with the si550 vcxo? for comparison highlighting power supply rejection (psr) advantage of si55x versus saw-based solutions.
SI570/si571 10 rev. 0.3 table 8. typical clk output phase noise (SI570) offset frequency (f) 120.00 mhz lvds 156.25 mhz lvpecl 622.08 mhz lvpecl units 100 hz 1khz 10 khz 100 khz 1mhz 10 mhz 100 mhz ?112 ?122 ?132 ?137 ?144 ?150 n/a ?105 ?122 ?128 ?135 ?144 ?147 n/a ?97 ?107 ?116 ?121 ?134 ?146 ?148 dbc/hz table 9. typical clk output phase noise (si571) offset frequency 74.25 mhz 90 ppm/v lvpecl 491.52 mhz 45 ppm/v lvpecl 622.08 mhz 135 ppm/v lvpecl units 100 hz 1khz 10 khz 100 khz 1mhz 10 mhz 100 mhz ?87 ?114 ?132 ?142 ?148 ?150 n/a ?75 ?100 ?116 ?124 ?135 ?146 ?147 ?65 ?90 ?109 ?121 ?134 ?146 ?147 dbc/hz table 10. absolute maximum ratings parameter symbol rating units supply voltage v dd ?0.5 to +3.8 volts input voltage v i ?0.5 to v dd + 0.3 volts storage temperature t s ?55 to +125 oc esd sensitivity (hbm, per jesd22-a114) esd >2500 volts soldering temperature (lead-free profile) t peak 260 oc soldering temperature time @ t peak (lead-free profile) t p 20?40 seconds notes: 1. stresses beyond the absolute maximum ratings may cause pe rmanent damage to the device. functional operation or specification compliance is not implied at these conditions. 2. the device is compliant with jedec j-std-020c. refer to si5xx packaging faq available for download at www.silabs.com/vcxo for further information, including soldering profiles.
SI570/si571 rev. 0.3 11 table 11. environmental compliance the SI570/571 meets the following qualification test requirements. parameter conditions/test method mechanical shock mil-std-883f, method 2002.3 b mechanical vibration mil-std-883f, method 2007.3 a solderability mil-std-8 83f, method 203.8 gross & fine leak mil-std-883f, method 1014.7 resistance to solvents mil-std-883f, method 2016 table 12. programming constraints (v dd = 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test co ndition min typ max unit output frequency cko f hs_div x n1 > = 6 10 ? 945 mhz hs_div x n1 = 5 n1 = 1 970 ? 1134 mhz hs_div = 4 n1 = 1 1.2125 ? 1.4175 ghz m and rfreq value lsb resolution m res 114.285 mhz 3rd overtone crystal ?0.09? ppb internal oscillator frequency f osc 4850 ? 5670 mhz unfreeze to newfreq delay ? ? 10 ms
SI570/si571 12 rev. 0.3 3. functional description the SI570 xo and the si571 vcxo are low-jitter, programmable oscillators idea lly suited for applications requiring multiple freque ncies. the si57x can be programmed to generate any output clock rate between 10 and 1.4 ghz with <1 ppb resolution. output jitter performance exceeds the strict requirements of high- speed communication system s including oc-48/oc- 192 and 10 gigabit ethernet. the si57x employs silicon laboratories? third- generation digital signal processing based phase- locked loop (dspll ? ) technology providing excellent jitter performance, digital programmability, and stability while requiring minimal external components. at the core of the si57x is a di gitally-controlled oscillator (dco) based on dspll technology that is driven by a digital frequency control word and produces a low-jitter output clock. (see "1. detailed block diagrams" on page 4.) 3.1. frequency programming summary the output frequency is determined by programming the output dividers (hs_div and n1) and the fine frequency control value (rfreq). the value programmed into rfreq is a high-resolution 38-bit value that adjusts the dco frequency in a range from 4.85 to 5.67 ghz. the out put of the dco is divided down by hs_div and n1 to produce the desired output frequency. the 38-bit length of rfreq provides an output frequency resolution of better than 1 ppb. 3.2. frequency programming details programming consists of the following basic steps: deriving the actual crystal frequency, choosing new output dividers (hs_div & n1), calculating a new frequency multiplier (rfreq), and writing the new frequency set into the device (hs_div, n1, and rfreq). 3.2.1. selecting the correct output dividers by listing all of the combinations of hs_div and n1, one can choose the output divider set with the lowest power within the allowed in ternal oscillator frequency range as specified in table 12. the sets of dividers should be sorted to minimize f osc for power dissipation and to minimize n1 divider's power consumption. silicon laboratories? si57 x software automatically provides this optimizati on and returns the smallest hs_div x n1 combination with the highest hs_div value. 3.2.2. calculating the reference frequency multi- plier (rfreq) rfreq is a binary representation of the reference frequency multiplier and is 38 bits in length. to convert from a decimal number to the binary number rfreq must be broken into two parts: the integer portion and the fractional portion. the first 10 most-significant-bits (msbs) of rfreq represent the integer portion, and the lower 28 least-significant-bits (lsb's) represent the fractional portion. the integer portion can be converted directly from decimal to binary (e.g. decimal 43 = hexadecimal 02bh--the leading nibble only occupies two bits of rfreq). the fractional portion should be made into an in teger by multiplying by 2 28 and truncating (or rounding) the result as follows: (e.g. 0.54587216*2^28 = 146531442.18730496; then, truncate to 146531442). the truncated value can then be converted to binary (e.g. decimal 146531442 = hexadecimal 8bbe472h). the resulting binary rfreq for 43.54587216 is 02b8bbe472h (02bh concatenated with 8bbe472h). 3.2.3. programming procedure the following steps must be followed to set a new output frequency: 1. read the frequency configuration (rfreq, hs_div, and n1) from the device after power-up or reset. 2. calculate the actual nominal crystal frequency (f xtal ) as: (f xtal =f 0 x hs_div x n1)/rfreq where f 0 is the nominal output frequency. 3. choose new output frequency (f 1 ). 4. choose the output dividers (hs_div and n1) for the new output frequency by ensuring the dco oscillation frequency (f osc ) is within the allowed internal oscillator freque ncy (see table 12) where: f osc =f 1 xhs_divxn1. 5. calculate the new crystal frequency multiplication ratio (rfreq 1 ) as: f osc =f xtal xrfreq. 6. freeze the dco (bit 5 of register 137). 7. write the frequency configuration (rfreq, hs_div, and n1). 8. unfreeze the dco and assert the newfreq bit (bit 6 of register 135) within the maximum delay specified in table 12, ?programming constraints,? on page 11. 3.2.4. programming procedure example the si57x-evb software can be used to generate examples as needed.
SI570/si571 rev. 0.3 13 3.3. i 2 c interface the control interface to the SI570 is an i 2 c-compatible 2-wire bus for bidirectional communication. the bus consists of a bidirectional serial data line (sda) and a serial clock input (scl). both lines must be connected to the positive supply via an external pullup. fast mode operation is supported for transfer rates up to 400 kbps as specified in the i 2 c-bus specification standard. figure 3 shows the command format for both read and write access. data is always sent msb first. the timing specifications and timing diagram for the i 2 c bus can be found in the i 2 c-bus specification standard (fast mode operation). the device i 2 c address is specified in the part number. figure 3. i 2 c command format adata adata p a 1 slave address s a byte address a 0 slave address s 1 from master to slave from slave to master a ? acknowledge (sda low) s ? start condition p ? stop condition write command read command address auto incremented after each data read or write p a data a data a byte address a 0 slave address s
SI570/si571 14 rev. 0.3 4. serial port registers note: any register not listed here is reserved and must no t be written. all bits are r/w unless otherwise noted. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7 high speed/ n1 dividers hs_div[2:0] n1[6:2] 8 reference frequenc y n1[1:0] rfreq[37:32] 9 reference frequency rfreq[31:24] 10 reference frequency rfreq[23:16] 11 reference frequency rfreq[15:8] 12 reference frequency rfreq[7:0] 135 reset/memory contro l rst_reg newfreq recall 137 freeze dco freeze dco
SI570/si571 rev. 0.3 15 register 7. high speed/n1 dividers bitd7d6d5d4d3d2d1d0 name hs_div[2:0] n1[6:2] type r/w r/w bit name function 7:5 hs_div[2:0] dco high speed divider. sets value for high speed divider that takes the dco output f osc as its clock input. 000 = 4 001 = 5 010 = 6 011 = 7 100 = not used. 101 = 9 110 = not used. 111 = 11 4:0 n1[6:2] clkout output divider. sets value for clkout output divider. a llowed values are [1] and [2, 4, 6, ..., 2 7 ]. illegal odd divider values will be rounde d up to the nearest even valu e. the value fo r the n1 reg- ister can be calculated by taking the divider ratio minus one. for example, to divide by 10, write 0001001 (9 decimal) to the n1 registers. 0000000 = 1 1111111 = 2 7 register 8. reference frequency bitd7d6d5d4d3d2d1d0 name n1[1:0] rfreq[37:32] type r/w r/w bit name function 7:6 n1[1:0] clkout output divider. sets value for clkout output divider. a llowed values are [1, 2, 4, 6, ..., 2 7 ]. illegal odd divider values will be rounded up to the neare st even value. the va lue for the n1 regis- ter can be calculated by taking the divider ratio minus one. for example, to divide by 10, write 0001001 (9 decimal) to the n1 registers. 0000000 = 1 1111111 = 2 7 5:0 rfreq[37:32] reference frequency. frequency control input to dco.
SI570/si571 16 rev. 0.3 register 9. reference frequency bitd7d6d5d4d3d2d1d0 name rfreq[31:24] type r/w bit name function 7:0 rfreq[31:24] reference frequency. frequency control input to dco. register 10. reference frequency bitd7d6d5d4d3d2d1d0 name rfreq[23:16] type r/w bit name function 7:0 rfreq[23:16] reference frequency. frequency control input to dco. register 11. reference frequency bitd7d6d5d4d3d2d1d0 name rfreq[15:8] type r/w bit name function 7:0 rfreq[15:8] reference frequency. frequency control input to dco.
SI570/si571 rev. 0.3 17 reset settings = 00xx xx00 register 12. reference frequency bitd7d6d5d4d3d2d1d0 name rfreq[7:0] type r/w bit name function 7:0 rfreq[7:0] reference frequency. frequency control input to dco. register 135. reset/memory control bit d7 d6 d5 d4 d3 d2 d1 d0 name rst_reg newfreq n/a recall type r/w r/w r/w r/w bit name function 7 rst_reg internal reset. 0 = normal operation. 1 = reset of all internal logic. output trista ted during reset. upon completion of internal logic reset, rst_reg is interna lly reset to zero. 6 newfreq new frequency applied. alerts the dspll that a new frequency co nfiguration has been a pplied. this bit will clear itself when the ne w frequency is applied. 5:1 n/a always zero. 0recall recall nvm into ram. 0 = no operation. 1 = write nvm bits into ram. bit is interna lly reset following comp letion of operation.
SI570/si571 18 rev. 0.3 reset settings = 00xx xx00 register 137. freeze dco bitd7d6 d5 d4d3d2d1d0 name freeze dco type r/w bit name function 7:6 reserved 5 freeze dco freeze dco. freezes the dspll so the frequency configuration can be modified. 4:0 reserved
SI570/si571 rev. 0.3 19 5. SI570 (xo) pin descriptions table 13. SI570 pin descriptions pin name type function 1 nc n/a no connect. 2 oe input output enable: see "7. ordering information" on page 21. 3 gnd ground electrical and case ground. 4 clk+ output oscillator output. 5 clk? (n/a for cmos) output complementary output (n/c for cmos). 6 v dd power power supply voltage. 7 sda bidirectional open drain i 2 c serial data. 8 scl input i 2 c serial clock. (top view) 1 2 3 6 5 4 nc gnd oe v dd clk+ clk? sda scl 8 7
SI570/si571 20 rev. 0.3 6. si571 (vcxo) pin descriptions table 14. si571 pin descriptions pin name type function 1 v c analog input control voltage 2 oe input output enable: see "7. ordering information" on page 21. 3 gnd ground electrical and case ground 4 clk+ output oscillator output 5 clk? (n/a for cmos) output complementary output (n/c for cmos) 6 v dd power power supply voltage 7 sda bidirectional open drain i 2 c serial data 8 scl input i 2 c serial clock (top view) 1 2 3 6 5 4 v c gnd oe v dd clk+ clk? sda scl 8 7
SI570/si571 rev. 0.3 21 7. ordering information the SI570/si571 supports a wide variety of options incl uding frequency range, start-up frequency, temperature stability, tuning slope, output format, and v dd . specific device configurations are programmed into the SI570/si571 at time of shipment. configurations are specified using the part number co nfiguration chart shown below. silicon labs provides a web browser-based part number conf iguration utility to simplif y this process. refer to www.silabs.com/vcxopartnumber to access this tool and for further ordering instructions. the SI570/si571 xo/ vcxo series is supplied in an industry-standard, rohs compliant, pb-free, 8-pad, 5 x 7 mm package. tape and reel packaging is an ordering option. figure 4. part number convention 570 programmable xo product family 57x x 1 st option code v dd output format output enable polarity a 3.3 lvpecl high b 3.3 lvds high c3.3cmos high d3.3cml high e 2.5 lvpecl high f 2.5 lvds high g2.5cmos high h2.5cml high j 1.8 cmos high k1.8cml high m 3.3 lvpecl low n3.3lvds low p3.3cmos low q3.3cml low r 2.5 lvpecl low s2.5lvds low t2.5cmos low u2.5cml low v1.8cmos low w1.8cml low note : cmos available to 160 mhz. 571 programmable vcxo product family r = tape & reel blank = trays operating temp range (c) g ?40 to +85 c device revision letter x d g r six-digit start-up frequency/i 2 c address designator the si57x supports a user-defined start-up frequency within the following bands of frequencies: 10?945 mhz, 970?1134 mhz, and 1213?1417 mhz. the start-up frequency must be in the same frequency range as that specified by the frequency grade 3 rd option code. the si57x supports a user-defined i 2 c 7-bit address. each unique start-up frequency/i 2 c address combination is assigned a six-digit numerical code. this code can be requested during the part number request process. refer to www.silabs.com/vcxopartnumber to request an si57x part number. x xxx xxx 3 rd option code frequency grade code frequency range supported (mhz) a 10-945, 970-1134, 1213-1417.5 b 10-810 c 10-215 2 nd option code temperature tuning slope minimum apr stability kv (ppm) for vdd @ code ppm (max) ppm/v (typ) 3.3 v 2.5 v 1.8 v a 100 180 100 75 25 b 100 90 30 note 6 note 6 c 50 180 150 125 75 d50 90 803025 e 20 45 25 note 6 note 6 f 50 135 100 75 50 g 20 356 375 300 235 h 20 180 185 145 105 j 20 135 130 104 70 k 100 356 295 220 155 m 20 33 12 note 6 note 6 notes: 1. for best jitter and phase noise performance, always choose the smallest kv that meets the application?s minimum apr requirements. unlike saw-based solutions which require higher higher kv values to account for their higher temperature dependence, the si55x series provides lower kv options to minimize noise coupling and jitter in real- world pll designs. see an255 and an266 for more information. 2. apr is the ability of a vcxo to track a signal over the product lifetime. a vcxo with an apr of 25 ppm is able to lock to a clock with a 25 ppm stability over 15 years over all operating conditions. 3. nominal pull range () = 0.5 x v dd x tuning slope. 4. nominal absolute pull range ( apr) = pull range ? stab ility ? lifetime aging = 0.5 x v dd x tuning slope ? stability ? 10 ppm 5. minimum apr values noted above include worst case values for all parameters. 6. combination not available. SI570 si571 2 nd option code code temperature stability (ppm, max, ) total stablility (ppm, max, ) a 50 61.5 b 20 31.5
SI570/si571 22 rev. 0.3 8. si57x mark specification figure 5 illustrates the mark specification for the si57x. table 15 lists the line information. figure 5. mark specification table 15. si57x top mark description line position description 1 1?10 ?silabs?+ part family number, 5xx (first 3 characters in part number) 2 1?10 SI570, si571: option1 + option2 + option3 + confignum(6) + temp 3 trace code position 1 pin 1 orientation mark (dot) position 2 product revision (d) position 3?6 tiny trace code (4 alphanumeric charac ters per assembly release instructions) position 7 year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) position 8?9 calendar work week number (1?53), to be assigned by assembly site position 10 ?+? to indicate pb-free and rohs-compliant silabs 123 123 4 5 6 r t t t t y w w + 1 2 3 4 5 6 7 8 9 0
SI570/si571 rev. 0.3 23 9. outline diagram and suggested pad layout figure 6 illustrates the package details for the SI570/si5 71. table 16 lists the values for the dimensions shown in the illustration. figure 6. SI570/si571 outline diagram table 16. package diagram dimensions (mm) dimension min nom max a 1.45 1.65 1.85 b1.21.41.6 c0.60 typ d 0.97 1.17 1.37 d 7.00 bsc d1 6.10 6.2 6.30 e 2.54 bsc e 5.00 bsc e1 4.30 4.40 4.50 l 1.07 1.27 1.47 m0.81.01.2 s 1.815 bsc r 0.7 ref aaa ? ? 0.15 bbb ? ? 0.15 ccc ? ? 0.10 ddd ? ? 0.10
SI570/si571 24 rev. 0.3 10. 8-pin pcb land pattern figure 7 illustrates the 8-pin pcb land pattern for the SI570/si571. table 17 lists the values for the dimensions shown in the illustration. figure 7. SI570/si571 pcb land pattern table 17. pcb land pattern dimensions (mm) dimension min max d2 5.08 ref d3 5.705 ref e 2.54 bsc e2 4.20 ref gd 0.84 ? ge 2.00 ? vd 8.20 ref ve 7.30 ref x1 1.70 typ x2 1.545 typ y1 2.15 ref y2 1.3 ref zd ? 6.78 ze ? 6.30 note: 1. dimensioning and tolerancing per the ansi y14.5m-1994 specification. 2. land pattern design follows ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). 4. controlling dimension is in millimeters (mm).
SI570/si571 rev. 0.3 25 d ocument c hange l ist revision 0.1 to revision 0.2 updated " description" on page 1. updated "1. detailed block diagrams" on page 4 for both xo and vcxo. updated the nominal control voltage in table 2, ?v c control voltage input,? on page 5. updated tables to reflect slight performance differences between SI570 and si571. added detail to the "3.2. frequency programming details" on page 12. revised "3.2.3. programming procedure" on page 12. procedure now requires use of two frequency configuration register sets. procedure now recommends disabling output at powerup to protect equipment not expecting the default output frequency. added second frequency configuration register set to the register tables. added frequency configuration select register. updated "7. ordering information" on page 21 to be consistent with the si55x series devices. revision 0.2 to revision 0.3 updated table 1, ?recommended operating conditions,? on page 5. device maintains stable operation over ?40 to +85 oc operating temperature range. supply current specifications updated. updated table 4, ?clk output levels and symmetry,? on page 7. updated lvds differential peak-peak swing specifications. updated table 5, ?clk output phase jitter (SI570),? on page 7. updated table 6, ?clk output phase jitter (si571),? on page 8. updated table 7, ?clk outp ut period jitter,? on page 9. revised period jitter specifications. updated table 10, ?absolute maximum ratings,? on page 10 to reflect the soldering temperature time at 260 oc is 20?40 sec per jedec j-std-020c. updated device programming procedure in section "3.2.3. programming procedure" on page 12. updated "7. ordering information" on page 21. changed ordering instructions to revision d. added "8. si57x mark specification" on page 22.
SI570/si571 26 rev. 0.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: vcxoinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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